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d a t a sh eet objective speci?cation file under integrated circuits, ic12 1999 aug 24 integrated circuits PCF8535 65 133 pixel matrix driver
1999 aug 24 2 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 contents 1 features 2 applications 3 general description 4 ordering information 5 block diagram 5.1 block diagram functions 5.1.1 oscillator 5.1.2 power-on reset 5.1.3 i 2 c-bus controller 5.1.4 input filters 5.1.5 display data ram 5.1.6 timing generator 5.1.7 address counter 5.1.8 display address counter 6 pinning 6.1 pin functions 6.1.1 r0 to r64 6.1.2 c0 to c132 6.1.3 v ss1 and v ss2 6.1.4 v dd1 to v dd3 6.1.5 v lcdout 6.1.6 v lcdin 6.1.7 v lcdsense 6.1.8 sda 6.1.9 sdaout 6.1.10 scl 6.1.11 sa0 and sa1 6.1.12 osc 6.1.13 res 6.1.14 t1, t2, t3, t4 and t5 7 functional description 7.1 reset 7.2 power-down 7.3 lcd voltage selector 7.4 oscillator 7.5 timing 7.6 column driver outputs 7.7 row driver outputs 7.8 drive waveforms 7.9 set multiplex rate 7.10 bias system 7.10.1 set bias system 7.11 temperature measurement 7.11.1 temperature read back 7.12 temperature compensation 7.12.1 temperature coefficients 7.13 v op 7.13.1 set v op value 7.14 voltage multiplier control 7.14.1 s[1:0] 7.15 addressing 7.15.1 input addressing 7.15.2 output addressing 7.16 instruction set 7.16.1 ram read/write command page 7.16.2 function and ram command page 7.16.3 display setting command page 7.16.4 hv-gen command page 7.16.5 special feature command page 7.16.6 instruction set 7.17 i 2 c-bus interface 7.17.1 characteristics of the i 2 c-bus 7.17.2 i 2 c-bus protocol 8 limiting values (provisional) 9 handling 10 dc characteristics 11 ac characteristics 12 reset timing 13 application information 14 bonding pad locations 15 device protection diagram 16 tray information 17 definitions 18 life support applications 19 purchase of philips i 2 c components 20 bare die disclaimer
1999 aug 24 3 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 1 features single-chip lcd controller/driver 65 row, 133 column outputs display data ram 65 133 bits 133 icons (last row is used for icons) fast mode i 2 c-bus interface (400 kbits/s) software selectable multiplex rates: 1:17,1:26,1:34,1:49and1:65 on-chip: C generation of intermediate lcd bias voltages C oscillator requires no external components (external clock also possible) C generation of v lcd . cmos compatible inputs software selectable bias configuration logic supply voltage range v dd1 to v ss1 4.5 to 5.5 v supply voltage range for high voltage part v dd2 and v dd3 to v ss2 and v ss3 4.5 to 5.5 v display supply voltage range v lcd to v ss : C mux rate 1 : 65: 8 to 16 v. low power consumption, suitable for battery operated systems internal power-on reset and/or external reset temperature read back available manufactured in n-well silicon gate cmos process. 2 applications automotive information systems telecommunication systems point-of-sale terminals instrumentation. 3 general description the PCF8535 is a low power cmos lcd row/column driver, designed to drive dot matrix graphic displays at multiplex rates of 1 : 17 , 1 : 26, 1 : 34, 1 : 49 and 1 : 65. furthermore, it can drive up to 133 icons. all necessary functions for the display are provided in a single chip, including on-chip generation of lcd bias voltages, resulting in a minimum of external components and low power consumption. the PCF8535 is compatible with most microcontrollers and communicates via an industry standard two-line bidirectional i 2 c-bus serial interface. all inputs are cmos compatible. 4 ordering information type number package name description version PCF8535u - chip with bumps in tray -
1999 aug 24 4 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 5 block diagram handbook, full pagewidth mgs669 display data ram matrix data ram data latches matrix latches column drivers c0 to c132 PCF8535 r0 to r64 row drivers command decoder address counter display address counter timing generator oscillator internal reset power-on reset res osc i 2 c-bus control input filters sa0 sa1 scl sda sdaout v lcdout v lcdsense v lcdin t1, t2, t3 t4, t5 65 v ss2 v ss1 v dd1 v dd2 v dd3 v lcd generator bias voltage generator 133 fig.1 block diagram.
1999 aug 24 5 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 5.1 block diagram functions 5.1.1 o scillator the on-chip oscillator provides the display clock for the system; it requires no external components. alternatively, an external display clock may be provided via the osc input. the osc input must be connected to v dd1 or v ss1 when not in use. during power-down additional current saving can be made if the external clock is disabled. 5.1.2 p ower - on reset the on-chip power-on reset initializes the chip after power-on or power failure. 5.1.3 i 2 c- bus controller the i 2 c-bus controller detects the i 2 c-bus protocol, slave address, commands and display data bytes. it performs the conversion of the data input (serial-to-parallel). the PCF8535 acts as an i 2 c-bus slave and therefore cannot initiate bus communication. 5.1.4 i nput filters input filters are provided to enhance noise immunity in electrically adverse environments; rc low-pass filters are provided on the sda, scl and res lines. 5.1.5 d isplay data ram the PCF8535 contains a 65 133 bit static ram which stores the display data. the ram is divided into 9 banks of 133 bytes. the last bank is used for icon data and is only one bit deep. during ram access, data is transferred to the ram via the i 2 c-bus interface. there is a direct correspondence between the x address and the column output number. 5.1.6 t iming generator the timing generator produces the various signals required to drive the internal circuitry. internal chip operation is not disturbed by operations on the data bus. 5.1.7 a ddress counter the address counter (ac) sends addresses to the display data ram (ddram) for writing. 5.1.8 d isplay address counter the display is generated by continuously shifting rows of ram data to the dot matrix lcd via the column outputs. the display status (all dots on or off, normal or inverse video) is set via the i 2 c-bus.
1999 aug 24 6 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 6 pinning 6.1 pin functions 6.1.1 r0 to r64 these pads output the display row signals. symbol pad description 1 dummy pad 2 bump/alignment mark 1 r0 to r15 3 to 18 lcd row driver outputs c0 to c132 19 to 151 lcd column driver outputs r47 to r33 152 to 166 lcd row driver outputs 167 bump/alignment mark 2 168 dummy pad r48 to r64 169 to 185 lcd row driver outputs; r64 is icon row 186 bump/alignment mark 3 187 to 189 dummy pad osc 190 oscillator v lcdin 191 to 196 lcd supply voltage v lcdout 197 to 203 voltage multiplier output v lcdsense 204 voltage multiplier regulation input (v lcd ) 205 and 206 dummy pad res 207 external reset input (active low) t3 208 test output 3 t2 209 test output 2 t1 210 test output 1 v dd2 211 to 218 supply voltage 2 v dd3 219 to 222 supply voltage 3 v dd1 223 to 228 supply voltage 1 229 dummy pad sda 230 and 231 i 2 c-bus serial data inputs sdaout 232 i 2 c-bus serial data output sa1 233 i 2 c-bus slave address input sa0 234 i 2 c-bus slave address input v ss2 235 to 242 ground 2 v ss1 243 to 250 ground 1 t5 251 test input 5 t4 252 test input 4 253 dummy pad scl 254 and 255 i 2 c-bus serial clock inputs 256 bump/alignment mark 4 r32 to r16 257 to 273 lcd row driver outputs
1999 aug 24 7 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 6.1.2 c0 to c132 these pads output the display column signals. 6.1.3 v ss1 and v ss2 v ss1 and v ss2 must be connected together. 6.1.4 v dd1 to v dd3 v dd1 is the logic supply. v dd2 and v dd3 are for the voltage multiplier. for split power supplies v dd2 and v dd3 must be connected together. if only one supply voltage is available, all three supplies must be connected together. 6.1.5 v lcdout if, in the application, an external v lcd is used, v lcdout must be left open-circuit; otherwise (if the internal voltage multiplier is enabled) the chip may be damaged. v lcdout should not be driven when v dd1 is below its minimum allowed value otherwise a low impedance path between v lcdout and v ss1 will exist. 6.1.6 v lcdin this is the v lcd supply for when an external v lcd is used. if the internal v lcd generator is used, then v lcdout and v lcdin must be connected together. v lcdin should not be driven when v dd1 is below its minimum allowed value, otherwise a low impedance path between v lcdin and v ss1 will exist. 6.1.7 v lcdsense this is the input to the internal voltage multiplier regulator. it must be connected to v lcdout when the internal voltage generator is used otherwise it may be left open-circuit. v lcdsence should not be driven when v dd1 is below its minimum allowed value, otherwise a low impedance path between v lcdsence and v ss1 will exist. 6.1.8 sda i 2 c-bus serial data input. 6.1.9 sdaout sdaout is the serial data acknowledge for the i 2 c-bus. by connecting sdaout to sda externally, the sda line becomes fully i 2 c-bus compatible. having the acknowledge output separated from the serial data line is advantageous in chip-on-glass (cog) applications. in cog applications where the track resistance from the sdaout pad to the system sda line can be significant, a potential divider is generated by the bus pull-up resistor and the indium tin oxide (ito) track resistance. it is possible that during the acknowledge cycle the PCF8535 will not be able to create a valid logic 0 level. by splitting the sda input from the sdaout output the device could be used in a mode that ignores the acknowledge bit. in cog applications where the acknowledge cycle is required or where read back is required, it is necessary to minimize the track resistance from the sdaout pad to the system sda line to guarantee a valid low level. 6.1.10 scl i 2 c-bus serial clock input. 6.1.11 sa0 and sa1 least significant bits of the i 2 c-bus slave address. table 1 slave address; see note 1 note 1. the slave address is a concatination of the following bits {01111, sa1, sa0 and r/ w}. 6.1.12 osc if the on-chip oscillator is used this input must be connected to v dd1 or v ss1 . 6.1.13 res external reset pad: when this pad is low the chip will be reset; see section 7.1. if an external reset is not required, this pad must be tied to v dd1 . timing for the res pad is given in chapter 12. 6.1.14 t1, t2, t3, t4 and t5 in applications t4 and t5 must be connected to v ss . t1, t2 and t3 are to be left open-circuit. sa1 and sa0 mode slave address 0 and 0 write 78h read 79h 0 and 1 write 7ah read 7bh 1 and 0 write 7ch read 7dh 1 and 1 write 7eh read 7fh
1999 aug 24 8 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 7 functional description the PCF8535 is a low power lcd driver designed to interface with microprocessors/microcontrollers and a wide variety of lcds. the host microprocessor/microcontroller and the PCF8535 are both connected to the i 2 c-bus. the sda and scl lines must be connected to the positive power supply via pull-up resistors. the internal oscillator requires no external components. the appropriate intermediate biasing voltage for the multiplexed lcd waveforms are generated on-chip. the only other connections required to complete the system are to the power supplies (v dd ,v ss and v lcd ) and suitable capacitors for decoupling v lcd and v dd . handbook, full pagewidth mgs670 host microprocessor/ microcontroller lcd panel v ss v dd(i2c) v lcd v dd1 to v dd3 v dd1, v dd3 v ss1 v ss2 v dd2 v ss1, v ss2 sda scl sa1 sa0 PCF8535 r pu r pu res 133 column drivers 65 row drivers fig.2 typical system configuration.
1999 aug 24 9 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 7.1 reset the PCF8535 has two reset modes; internal power-on reset or external reset. reset initiated from either the res pad or the internal power-on reset block will initialize the chip to the following starting condition: power-down mode (pd = 1) horizontal addressing (v = 0); no mirror x or y (mx = 0 and my = 0) display blank (d = 0 an de=0) address counter x[6:0] = 0, y[2:0] = 0 and xm 0 =0 bias system bs[2:0] = 0 multiplex rate m[2:0] = 0 (mux rat e1:17) temperature control mode tc[2:0] = 0 hv-gen control, hve = 0 the hv generator is switched off, prs = 0 and s[1:0] = 00 v lcdout is equal to 0 v ram data is unchanged (note: ram data is undefined after power-up) all row and column outputs are set to v ss (display off) trs and brs are set to zero direct mode is disabled (dm = 0) internal oscillator is selected, but not running (ec = 0) bias current set to low current mode (ib = 0). 7.2 power-down during power-down all static currents are switched off (no internal oscillator, no timing and no lcd segment drive system) and all lcd outputs are internally connected to v ss . the serial bus function remains active. 7.3 lcd voltage selector the practical value for v op is determined by equating v off(rms) with defined lcd threshold voltage (v th ), typically when the lcd exhibits approximately 10% contrast. 7.4 oscillator the internal logic operation and the multi-level drive signals of the PCF8535 are clocked by the built-in rc oscillator. no external components are required. 7.5 timing the timing of the PCF8535 organizes the internal data flow of the device. the timing also generates the lcd frame frequency which is derived from the clock frequency generated in the internal clock generator. 7.6 column driver outputs the lcd drive section includes 133 column outputs (c0 to c132) which should be connected directly to the lcd. the column output signals are generated in accordance with the multiplexed row signals and with the data in the display latch. when less than 133 columns are required the unused column outputs should be left open-circuit. 7.7 row driver outputs the lcd drive section includes 65 row outputs (r0 to r64) which should be connected directly to the lcd. the row output signals are generated in accordance with the selected lcd drive mode. if lower mux rates or less than 65 rows are required, the unused outputs should be left open-circuit.
1999 aug 24 10 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 7.8 drive waveforms mgs671 row 0 r0 (t) row 1 r1 (t) col 0 c0 (t) col 1 c1 (t) 0 v 0 v v 3 - v ss frame n frame n + 1 01234567 8... ... 64 01234567 8... ... 64 v state1 (t) v state1 (t) v state2 (t) v lcd v 2 v 3 v 4 v 5 v ss v lcd v 2 v 3 v 4 v 5 v ss v lcd v 2 v 3 v 4 v 5 v ss v lcd v 2 v 3 v 4 v 5 v ss v lcd - v ss v lcd - v 2 v 4 - v 5 v ss - v 5 v 4 - v lcd v 3 - v ss v ss - v lcd 0 v 0 v v 3 - v ss v state2 (t) v lcd - v ss v lcd - v 2 v 4 - v 5 v 4 - v lcd v 3 - v ss v ss - v 5 v ss - v lcd fig.3 typical lcd driver waveforms. v state1 (t) = c1(t) - r0(t). v state2 (t) = c1(t) - r1(t).
1999 aug 24 11 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 7.9 set multiplex rate the PCF8535 can be used to drive displays of varying sizes. the multiplex mode selected controls which rows are used. in all cases, the last row is always driven and is intended for icons. if top row swap (trs) is at logic 1 then the icon row will be output on pad r48. m[2:0] selects the multiplex rate (see table 2). table 2 multiplex rates 7.10 bias system 7.10.1 s et bias system the bias voltage levels are set in the ratio of r - r - nr - r - r. different multiplex rates require different factors n. this is programmed by bs[2:0]. for optimum bias values, n can be calculated from: changing the bias system from the optimum will have a consequence on the contrast and viewing angle. one reason to come away from the optimum would be to reduce the required v op . a compromise between contrast and v op must be found for any particular application. table 3 programming the required bias system m[2] m[1] m[0] multiplex rate active rows 0 0 0 1 : 17 r0 to r15 and r64 0 0 1 1 : 26 r0 to r24 and r64 0 1 0 1 : 34 r0 to r32 and r64 0 1 1 1 : 49 r0 to r47 and r64 1 0 0 1:65 r0tor64 101 - 111 do not use - bs[2] bs[1] bs[0] n bias mode typical mux rates 0007 1 / 11 1 : 100 0016 1 / 10 1:80 0105 1 / 9 1:65 0114 1 / 8 1:49 1003 1 / 7 1:33 1012 1 / 6 1:26 1101 1 / 5 1:17 1110 1 / 4 1:9 n mux rate 3 C =
1999 aug 24 12 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 table 4 example of lcd bias voltage for 1 / 7 bias, n = 3 7.11 temperature measurement 7.11.1 t emperature read back the PCF8535 has an in-built temperature sensor. for power saving, the sensor should only be enabled when a measurement is required. it will not operate in power-down mode. the temperature read back requires a clock to operate. normally the internal clock is used but, if the device is operating from an external clock, then this must be present for the measurement to work. v dd2 and v dd3 must also be applied. a measurement is initialized by setting the sm bit. once started the sm bit will be automatically cleared. an internal oscillator will be initialized and allowed to warm-up for approximately 2 frame periods. after this the measurement starts and lasts for a maximum of 2 frame periods. temperature data is returned via a status register. during the measurement the register will contain zero. once the measurement is completed the register will be updated with the current temperature (non zero value). because the i 2 c-bus interface is asynchronous to the temperature measurement, read back prior to the end of the measurement is not guaranteed. if this mode is required the register should be read twice to validate the data. the ideal temperature read-out can be calculated as follows; (1) where t is the on-chip temperature in c and c is the conversion constant; c = 1.17 c/lsb. to improve the accuracy of the temperature measurement a calibration is recommended during the assembly of the final product. for calibrating the temperature read-out a measurement must be taken at a defined temperature. the offset between the ideal read-out and the actual result has to be stored into a non-volatile register (e.g. eeprom); (2) where tr meas is the actual temperature read-out of the PCF8535. the calibrated temperature read-out can be calculated for each measurement as follows: (3) the accuracy after the calibration is 6.7% (plus 1 lsb) of the difference between the current temperature and the calibration temperature. for this reason a calibration at or near the most sensitive temperature for the display is recommended. e.g. for a calibration at 25 c with the current temperature at - 20 c, the absolute error may be calculated as: absolute error = 0.067 (25 c -- 20 c) = 3 c+ 1 lsb = 4.17 c. 7.12 temperature compensation 7.12.1 t emperature coefficients due to the temperature dependency of the liquid crystals viscosity the lcd controlling voltage, v must be increased at lower temperatures to maintain optimum contrast. figure 4 shows v lcd as a function of temperature for a typical high multiplex rate liquid. in the PCF8535 the temperature coefficient of v lcd can be selected from 8 values by setting bits tc[2:0], see table 5. symbol bias voltage for 1 / 7 bias v1 v lcd v2 6 / 7 v lcd v3 5 / 7 v lcd v4 2 / 7 v lcd v5 1 / 7 v lcd v6 v ss tr ideal 128 t 27 c C () 1 c -- - + = offset tr ideal tr meas C = tr cal tr meas offset + =
1999 aug 24 13 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 handbook, halfpage mgs473 t v lcd 0 c fig.4 v lcd as function of liquid crystal temperature (typical values). table 5 selectable temperature coef?cients 7.13 v op 7.13.1 s et v op value the voltage at the reference temperature can be calculated as: [v lcd (t=t cut )] (4) the operating voltage, v op , can be set by software. the generated voltage is dependent on the temperature, programmed temperature coefficient (tc) and the programmed voltage at the reference temperature (t cut ): (5) the values for t cut , a and b are given in table 6. the maximum voltage that can be generated is dependent on the voltage v dd2 and the display load current. two overlapping v op ranges are selectable via the command page hv-gen control, see fig.5. the low range offers programming from 4.5 to 10.215 v, with the high range from 10.215 to 15.93 v at the cut point temperature, t cut . care must be taken, when using temperature coefficients, that the programmed voltage does not exceed the maximum allowed v lcd voltage, see chapter 10. for a particular liquid, the optimum v lcd can be calculated for a given multiplex rate. for a mux rate of 1 : 65, the optimum operating voltage of the liquid can be calculated as: (6) where v th is the threshold voltage of the liquid crystal material used. table 6 values for parameters of the hv generator programming tc[2] tc[1] tc[0] tc value unit 000 0 1/ c 001 - 0.44 10 - 3 1/ c 010 - 1.10 10 - 3 1/ c 011 - 1.45 10 - 3 1/ c 100 - 1.91 10 - 3 1/ c 101 - 2.15 10 - 3 1/ c 110 - 2.32 10 - 3 1/ c 111 - 2.74 10 - 3 1/ c v lcd tcut () av op b + () = v lcd av op b + () 1tt cut C () tc () + () = symbol bits value unit a prs = 0 4.5 v prs = 1 10.215 v b 0.045 v t cut 27 c v lcd 165 + 21 1 65 ---------- C ? ?? --------------------------------------- v th 6.85 v th = =
1999 aug 24 14 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 handbook, full pagewidth mgs472 00 01 02 a v lcd 03 04 05 06 . . . 5f 6f 7f 00 01 02 03 04 05 06 . . . 5f 6f 7f b low high fig.5 v op programming of PCF8535. v op [6:0] programming (00h to 7fh, programming range low and high). 7.14 voltage multiplier control 7.14.1 s[1:0] the PCF8535 incorporates a software configurable voltage multiplier. after reset ( res) the voltage multiplier is set to 2 v dd2 . other voltage multiplier factors are set via the hv-gen command page. before switching on the charge pump, the charge pump has to be pre-charged using the following sequence. a starting state of hve = 0, dof = 0, pd = 1 and dm = 0 is assumed. a small delay between steps is indicated. the recommended wait period is 20 m s per 100 nf of capacitance on v lcd1 . 1. set dm = 1 and pd = 0 2. delay 3. set the multiplication factor to 2 by setting s[1:0] = 00 4. set the required v op and prs. 5. set hve = 1 to switch-on the charge pump with a multiplication factor of 2 6. delay 7. increase the number of stages, one at a time, with a delay between each until the required level is achieved. table 7 hv generator multiplication factor s[1] s[0] multiplication factor 00 2 v dd2 01 3 v dd2 10 4 v dd2 11 5 v dd2
1999 aug 24 15 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 7.15 addressing addressing of the ram can be split into two parts; input addressing and output addressing. input addressing is concerned with writing data into the ram. output addressing is almost entirely automatic and taken care of by the device, however, it is possible to affect the output mode. 7.15.1 i nput addressing data is down loaded byte wise into the ram matrix of the PCF8535 as indicated in figs 6 to 10. the display ram has a matrix of 65 133 bits. the columns are addressed by a combination of the x address pointer and the x-ram page pointer, whilst the rows addressed in groups of 8 by the y address pointer. the x address pointer has a range of 0 to 127 (7fh). its range can be extended by the x-ram page pointer, xm 0 . the y address pointer has a range of 0 to 8 (08h). the PCF8535 is limited to 133 columns by 65 rows, addressing the ram outside of this area is not allowed. table 8 effect of x-ram page pointer x address pointer x-ram page pointer xm 0 addressed column mx = 0 addressed column mx = 1 0 0 c0 c132 1 0 c1 c131 2 0 c2 c130 :::: 125 0 c125 c7 126 0 c126 c6 127 0 c127 c5 0 1 c128 c4 1 1 c129 c3 :::: 4 1 c132 c0 handbook, full pagewidth mgs673 msb lsb banks 1 to 7 use the entire byte bank 8 is only 1 bit deep and uses the msb 0 xm 0 = 1 xm 0 = 0 1 2 3 4 5 6 7 8 .. .. .. .. lsb msb 0 1 2 3 4 0 1 2 3 4 123 124 125 126 119 120 121 122 127 y address x address icon data 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 fig.6 ram format, input addressing.
1999 aug 24 16 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 top of lcd r0 r8 r16 r24 r56 r64 mgs674 bank 0 bank 1 bank 2 bank 3 bank 7 bank 8 lcd msb lsb data byte in location y = 7, x = 0, mx 0 = 0 (mx = 0, my = 0) msb lsb data byte in location x = 0, y = 0, mx 0 = 0 (mx = 0, my = 0) fig.7 ddram to display mapping.
1999 aug 24 17 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 two automated addressing modes are available; vertical addressing (v = 1) and horizontal addressing (v = 0). these modes change the way in which the auto-incrementing of the address pointers is handled and are independent of multiplex rate. the auto-incrementing works in a way so as to aid filling of the entire ram. it is not a prerequisite of operation that the entire ram is filled; in lower multiplex modes not all of the ram will be needed. for these multiplex rates, use of horizontal addressing mode (v = 0) is recommended. addressing the icon row is a special case as these ram locations are not automatically accessed. these locations must be explicitly addressed by setting the y address pointer to 8. the y address pointer does not auto-increment when the x address over or underflows, it stays set to 8. writing icon data is independent of the vertical and horizontal addressing mode, but is effected by the mirror x bit as described in sections 7.15.1.2 and 7.15.1.3. the addressing modes may be further modified by the mirror x bit mx. this bit causes the data to be written into the ram from right to left instead of the normal left to right. this effectively flips the display about the y axis. the mx bit affects the mode of writing into the ram, changing the mx bit after ram data is written will not flip the display. 7.15.1.1 vertical addressing: non-mirrored; v = 1 and mx = 0 in the vertical addressing mode data is written top to bottom and left to right. here, the y counter will auto-increment from 0 to 7 and then wrap around to 0 (see fig.8). on each wrap over, the x counter will increment to address the next column. when the x counter wraps over from 127 to 0, the xm 0 bit will be set. the last address accessible is y = 7, x = 4 and xm 0 = 1; after this access the counter will wrap around to y = 0, x = 0 and xm 0 =0. handbook, full pagewidth mgs675 byte number byte order for icon data 0 xm 0 = 1 xm 0 = 0 1 2 3 4 5 6 7 8 .. .. .. .. 0 1 2 3 4 0 1 2 3 4 123 124 125 126 119 120 121 122 127 128 129 130 131 132 123 124 125 126 119 120 121 122 127 1031 1063 1015 1023 1030 1062 1014 1022 1029 1061 1013 1021 1028 1060 1012 1020 1027 .... .... 1019 1026 1018 1025 1017 1024 .... 1035 1034 1033 1032 1016 y address x address icon data 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 076543210 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 .... 26 25 24 1 2 12 13 14 15 16 17 18 19 20 21 22 23 24 fig.8 sequence of writing data bytes into the ram with normal vertical addressing (v = 1 and mx = 0).
1999 aug 24 18 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 7.15.1.2 vertical addressing: mirrored; v = 1 and mx = 1 it is also possible to write data from right to left, instead of from the normal left to right, still going top to bottom. in t he mirrored vertical addressing mode the y counter will auto-increment from 0 to 7 and then wrap around to 0 (see fig.9). on each wrap-over, the x counter will decrement to address the preceding column. the xm 0 bit will be automatically toggled each time the x address counter wraps over from 0. the last address accessible is y = 7, x = 0 and xm 0 =0; after this access the counter will wrap around to y = 0, x = 4 and xm 0 =1. handbook, full pagewidth mgs676 byte number byte order for icon data 0 xm 0 = 1 xm 0 = 0 1 2 3 4 5 6 7 8 4 3 2 1 0 9 8 7 6 13 12 11 10 5 39 31 7 47 38 30 6 46 37 5 45 36 432 10 44 35 .... 43 34 42 32 .... .... 9 33 41 50 49 1 8 0 40 48 y address icon data 132 1063 1062 1061 1060 1059 1058 1057 1056 1055 1054 1053 1052 .... 131 130 120 119 118 117 116 115 114 113 112 111 110 109 108 .. .. .. .. 0 1 2 3 4 0 1 2 3 4 123 124 125 126 119 120 121 122 127 x address 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 fig.9 sequence of writing data bytes into the ram with mirrored vertical addressing (v = 1 and mx = 1).
1999 aug 24 19 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 7.15.1.3 horizontal addressing: non-mirrored; v = 0 and mx = 0 in horizontal addressing mode data is written from left to right and top to bottom. here, the x counter will auto-increment from 0 to 127, set the xm 0 , then count 0 to 4 before wrapping around to 0 and clearing the xm 0 bit (see fig.10). on each wrap-over, the y counter will increment. the last address accessible is y = 7, x = 4 and xm 0 = 1; after this access the counter will wrap around to y = 0, x = 0 and xm 0 =0. handbook, full pagewidth mgs677 byte number byte order for icon data 0 xm 0 = 1 xm 0 = 0 1 2 3 4 5 6 7 8 .. .. .. .. 0 1 2 3 4 0 1 2 3 4 123 124 125 126 119 120 121 122 127 128 129 130 131 132 123 124 125 126 119 120 121 122 127 1059 1060 1061 1062 927 928 929 1063 1057 1056 1055 1054 1053 1052 1051 1050 1058 926 930 924 .... 925 128 129 130 131 132 127 126 125 124 123 122 121 120 119 y address x address icon data 5 6 7 8 9 10 11 934 935 936 937 938 939 940 941 942 12 13 14 15 16 17 18 19 20 21 22 23 24 0 931 133 0 932 134 1 933 135 2 136 .... 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 12 13 14 15 16 17 18 19 20 21 22 23 24 943 944 945 946 947 948 949 950 951 952 953 954 955 fig.10 sequence of writing data bytes into the ram with normal horizontal addressing (v = 0 and mx = 0).
1999 aug 24 20 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 7.15.1.4 horizontal addressing: mirrored; v = 0 and mx = 1 it is also possible to write data from right to left, instead of from the normal left to right, still going top to bottom. in t he mirrored horizontal addressing mode the x counter will auto-decrement from 4 to 0, clear the xm 0 , then count 127 to 0 before wrapping around to 4 and setting the xm 0 bit (see fig.10). on each wrap-over, the y counter will increment. the last address accessible is y = 7, x = 0 and xm 0 = 0; after this access the counter will wrap around to y = 0, x = 4 and xm 0 =1. handbook, full pagewidth mgs678 byte number byte order for icon data 0 xm 0 = 1 xm 0 = 0 1 2 3 4 5 6 7 8 4 3 2 1 0 9 8 7 6 13 12 11 10 5 935 934 933 932 931 937 938 939 940 941 942 943 944 936 .... 4 136 134 135 133 3 2 1 0 5 6 7 8 9 10 11 12 13 y address icon data 1060 1059 1058 1057 1056 1055 1054 1053 1052 132 1063 930 132 1062 929 131 1061 928 927 926 925 924 .... 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 131 130 120 119 118 117 116 115 114 113 112 111 110 109 108 1051 1050 1049 1048 1047 1046 1045 1044 1043 1042 1041 1040 1039 .. .. .. .. 0 1 2 3 4 0 1 2 3 4 123 124 125 126 119 120 121 122 127 x address 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 fig.11 sequence of writing data bytes into the ram with mirrored horizontal addressing (v = 0 and mx = 1).
1999 aug 24 21 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 7.15.2 o utput addressing the output addressing of the ram is done automatically in accordance with the currently selected multiplex rate. normally the user would not need to make any alterations to the addressing. there are, however, circumstances pertaining to various connectivity of the device on a glass that would benefit from some in-built functionality. three modes exist that enable the user to modify the output addressing, namely: 1. my, mirror the y axis. this mode effectively flips the display about the x axis, resulting in an upside down display. the effect is observable immediately the bit is modified. this is useful if the device is to be mounted above the display area instead of below. 2. bottom row swap (brs). this mode swaps the order of the rows on the bottom (1) edge of the chip. this is useful to aide routing to the display when it is not possible to pass tracks under the device; a typical example would be in tape carrier package. this mode is often used in conjunction with trs. 3. top row swap (trs). as with brs, but swaps the order of rows on the top (1) edge of the chip. 7.15.2.1 mirror y, my as described above, the y axis is mirrored in the x axis. (1) the top edge is de?ned as the edge containing the user interface connections. the bottom edge is the opposing edge. handbook, full pagewidth mgs679 .. c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 c20 c21 c22 c23 c24 c25 c26 c27 c28 y axis y axis r0 r1 r2 r3 r4 r5 r6 r7 r8 r55 r56 r57 r58 r59 r60 r61 r62 r63 r64 .. .. r64 my = 0 my = 1 mirror ... icons ... ... icons ... fig.12 mirror y behaviour (mux rate 1 : 65).
1999 aug 24 22 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 7.15.2.2 bottom row swap here the order of the row pads is modified. each block of rows is swapped about its local y axis. 7.15.2.3 top row swap here the order of the row pads is modified. each block of rows is swapped about its local y axis. handbook, full pagewidth mgs680 r16 r32 r64 r48 r15 r0 columns interface r33 r47 fig.13 bottom row swap. handbook, full pagewidth mgs681 r32 r16 r48 r64 r0 r15 columns interface r47 r33 fig.14 top row swap.
1999 aug 24 23 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 7.15.2.4 output row order the order in which the rows are activated is a function of bits my, trs, brs and the selected multiplex mode. tables 9 to 12 give the order in which the rows are activated. in all cases, the ram is accessed in a linear fashion, starting at zero with a jump to the last row for the icon data. table 9 row order for brs = 0 and trs = 0 table 10 row order for brs = 1 and trs = 0 table 11 row order for brs = 0 and trs = 1 table 12 row order for brs = 1 and trs = 1 multiplex mode my = 0 my = 1 1 : 17 r0 to r15 and r64 r15 to r0 and r64 1 : 26 r0 to r24 and r64 r24 to r0 and r64 1 : 33 r0 to r31 and r64 r31 to r0 and r64 1 : 49 r0 to r47 and r64 r47 to r0 and r64 1 : 65 r0 to r64 r63 to r0 and r64 multiplex mode my = 0 my = 1 1 : 17 r15 to r0 and r64 r0 to r15 and r64 1 : 26 r15 to r0, r16 to r24 and r64 r24 to r16, r0 to r15 and r64 1 : 33 r15 to r0, r16 to r31 and r64 r31 to r16, r0 to r15 and r64 1 : 49 r15 to r0, r16 to r32, r47 to r33 and r64 r33 to r47, r32 to r16, r0 to r15 and r64 1 : 65 r15 to r0, r16 to r32, r47 to r33 and r48 to r64 r63 to r48, r33 to r47, r32 to r16, r0 to r15 and r64 multiplex mode my = 0 my = 1 1 : 17 r0 to r15 and r48 r15 to r0 and r48 1 : 26 r0 to r15, r32 to r24 and r48 r24 to r32, r15 to r0 and r48 1 : 33 r0 to r15, r32 to r17 and r48 r17 to r32, r15 to r0 and r48 1 : 49 r0 to r15, r32 to r16, r33 to r47 and r48 r47 to r33, r16 to r32, r15 to r0 and r48 1 : 65 r0 to r15, r32 to r16, r33 to r47 and r64 to r48 r49 to r64, r47 to r33, r16 to r32, r15 to r0 and r48 multiplex mode my = 0 my = 1 1 : 17 r15 to r0 and r48 r0 to r15 and r48 1 : 26 r15 to r0, r32 to r24 and r48 r0 to r15, r32 to r24 and r48 1 : 33 r15 to r0, r32 to r17 and r48 r0 to r15, r17 to r32 and r48 1 : 49 r15 to r0, r32 to r16, r47 to r33 and r48 r0 to r15, r16 to r32, r33 to r47 and r48 1 : 65 r15 to r0, r32 to r16, r47 to r33 and r64 to r48 r0 to r15, r16 to r32, r33 to r47, r47 to r64 and r48
1999 aug 24 24 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 7.16 instruction set data accesses to the PCF8535 can be broken down into two areas, those that define the operating mode of the device and those that fill the display ram; the distinction being the d/ c bit. when the d/ c bit is at logic 0, the chip will respond to instructions as defined in table 16. when the d/ c bit is at logic 1, the chip will store data into the ram. data may be written to the chip that is independent to the presence of the display clock. there are 4 instruction types. those which: 1. define PCF8535 functions such as display configuration, etc. 2. set internal ram addresses 3. perform data transfer with internal ram 4. others. in normal use, category 3 instructions are the most frequently used. to lessen the mpu program load, automatic incrementing by one of the internal ram address pointers after each data write is implemented. the instruction set is broken down into several pages, each command page being individually addressed via the h[2:0] bits. 7.16.1 ram read / write command page this page is special in that it is accessible independently of the h bits. this page is mainly used as a stepping stone to other pages. sending the default h[2:0] command will cause an immediate step to the function and ram command page which will allow the h[2:0] bits to be set. 7.16.2 f unction and ram command page 7.16.2.1 command page setting h[2:0] will move the user immediately to the required command page. pages not listed should not be accessed as the behaviour is not defined. 7.16.2.2 function set pd when pd = 1, the lcd driver is in power-down mode: all lcd outputs at v ss oscillator off v lcdin may be disconnected i 2 c-bus interface accesses are possible ram contents are not cleared; ram data can be written register settings remain unchanged. v when v = 0, horizontal addressing is selected. when v = 1, vertical addressing is selected. the behaviour is described in section 7.15. 7.16.2.3 ram page the xm 0 bit extends the ram into a second page. the bit may be considered to be the most significant bit (msb) of an 8-bit x address. the behaviour is described in section 7.15. 7.16.2.4 set y address the y address is used as a pointer to the ram for ram writing. the range is 0 to 8. each bank corresponds to a set of 8 rows, the only exception being bank 8, which contains the icon data and is only 1-bit deep; see table 13. table 13 y address pointer y[3] y[2] y[1] y[0] bank rows 0000 bank 0 r0 to r7 0001 bank 1 r8 to r15 0010 bank 2 r16 to r23 0011 bank 3 r24 to r31 0100 bank 4 r32 to r39 0101 bank 5 r40 to r47 0110 bank 6 r48 to r55 0111 bank 7 r56 to r63 1000 bank 8 (icons) r64
1999 aug 24 25 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 7.16.2.5 set x address the x address is used as a pointer to the ram for ram writing. the range of x is 0 to 127 (7fh) and may be extended by the xm 0 bit. the combined value of xm 0 and x address directly corresponds to the display column number when mx = 0 and corresponds to the inverse display column number when mx = 1; see table 14. table 14 x address pointer 7.16.3 d isplay setting command page 7.16.3.1 display control the d and e bits set the display mode as given in table 15. table 15 display control 7.16.3.2 external display control mirror x and mirror y have the effect of flipping the display left to right or top to bottom respectively. mx works by changing the order data that is written into the ram. as such, the effects of toggling mx will only be seen after data is written into the ram. my works by reversing the order that column data is accessed relative to the row outputs. the effect of toggling my will be seen immediately. the behaviour of both of these bits is further described in section 7.15. 7.16.3.3 bias system bs[2:0] sets the bias system; see section 7.10. 7.16.3.4 display size physically large displays require stronger drivers. bit ib enables the user to select a stronger driving mode and should be used if suitable display quality can not be achieved with the default setting. 7.16.3.5 multiplex rate m[2:0] sets the multiplex rate; see section 7.9. 7.16.4 hv- gen command page 7.16.4.1 hv-gen control prs programmable charge pump range select. this bit defines whether the programmed voltage for v op is in the low or the high range. the behaviour of this bit is further described in section 7.13. hve high voltage generator enable. when set to logic 0, the charge pump is disabled. when set to logic 1, the charge pump is enabled. 7.16.4.2 hv-gen stages s[1:0] set the multiplication factor of the charge pump ranging from times 2 to times 5. the behaviour of these bits is further described in section 7.14. 7.16.4.3 temperature coef?cients tc[2:0] set the required temperature coefficient. the behaviour of these bits is further described in section 7.12. 7.16.4.4 temperature measurement control the sm bit is used to initiate a temperature measurement. the sm bit is automatically cleared at the end of the measurement. the behaviour of this bit is further described in section 7.11. 7.16.4.5 v lcd control v op [6:0] sets the required operating voltage for the display. xm 0 , x[6:0] addressed column, mx = 0 addressed column, mx = 1 0 c0 c132 1 c1 c131 2 c2 c130 3 c3 c129 :: : 129 c129 c3 130 c130 c2 131 c131 c1 132 c132 c0 d e mode 0 0 display blank 1 0 normal mode 0 1 all display segments on 1 1 inverse video
1999 aug 24 26 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 7.16.5 s pecial feature command page 7.16.5.1 state control dm direct mode allows v lcdout to be sourced directly from v dd2 . this may be useful in systems where v dd is to be used for v lcd . dof display off will turn off all internal analog circuitry that is not required for temperature measurement. as a consequence the display will be turned off. this mode is only required if temperature measurements are required whilst in power-down mode. 7.16.5.2 oscillator setting the internal oscillator may be disabled and the source clock for the display derived from the osc pad. it is important to remember that lcds are damaged by dc voltages and that the clock, whether derived internally or externally, should never be disabled whilst the display is active. the internal oscillator is switched off during power-down mode. when using an external clock and disabling it during power-down mode will further reduce the standby current. if it is not possible to disable it externally then it is worth noting that by selecting the internal clock, which is disabled during power-down mode, the same effect may be achieved. 7.16.5.3 cog/tcp the chip may be mounted on either a glass, foil or tape carrier package. for these applications, different organizations of the row pads are required to negate the necessity of routing under the device. the trs and brs allow for this swapping. the behaviour of both of these bits is further described in section 7.15. 7.16.6 i nstruction set table 16 instruction set instruction d/ cr/ w (1) i 2 c-bus command byte i 2 c-bus commands db7 db6 db5 db4 db3 db2 db1 db0 h[2:0] = xxx; ram read/write command page write data 1 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 writes data to display ram read status 0 1 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 returns result of temperature measurement nop 00 00000000no operation default h[2:0] 0 0 0 0 000001 jump to h[2:0] = 111 h[2:0] = 111; function and ram command page command page 0 0 0 0 001h 2 h 1 h 0 select command page function set 0 0 0 0 010pdv0pow er-down control, data entry mode ram page 0 0 0 0 100xm 0 0 0 set ram page for x address set y address of ram 00 0100y 3 y 2 y 1 y 0 sets y address of ram 0 y 8 set x address of ram 00 1x 6 x 5 x 4 x 3 x 2 x 1 x 0 sets x address of ram 0 x 127
1999 aug 24 27 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 note 1. r/ w is set in the slave address. h[2:0] = 110; display setting command page display control 0 0 0 0 0001de sets display mode external display control 00 00001mxmy0 mirror x, mirror y bias system 0 0 0 0 010bs 2 bs 1 bs 0 set bias system display size 0 0 0 0 100ib00 set current for bias system multiplex rate 0 0 1 0 000m 2 m 1 m 0 set multiplex rate h[2:0] = 101; hv-gen command page hv-gen control 0 0 0 0 0001prshvev lcd range, enable/disable hv-gen hv-gen stages 0 0 0 0 0010s 1 s 0 # of hv-gen voltage multiplication temperature coef?cients 00 00010tc 2 tc 1 tc 0 set temperature coef?cient temperature measurement control 00 0010000sm start temperature measurement v lcd control 0 0 1 v op6 v op5 v op4 v op3 v op2 v op1 v op0 set v lcd register 0 v lcd 127 h[2:0] = 011; special feature command page state control 0 0 0 0 0001dofdm display off, direct mode oscillator setting 0 0 0 0 0010ec0 enable/disable the internal oscillator cog/tcp 0 0 0 1 0 trs brs 0 0 0 top row swap, bottom row swap instruction d/ cr/ w (1) i 2 c-bus command byte i 2 c-bus commands db7 db6 db5 db4 db3 db2 db1 db0
1999 aug 24 28 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 table 17 description of the symbols used in table 16 note 1. conditional on other bits. table 18 priority behaviour of bits pd, dof, hve and dm; note 1 note 1. x = dont care state. bit 0 1 pd chip is active chip is in power-down mode v horizontal addressing vertical addressing hve voltage multiplier disabled voltage multiplier enabled prs v lcd programming range low v lcd programming range high sm no measurement start measurement mx no x mirror mirror x my no y mirror mirror y trs top row swap inactive top row swap active brs bottom row swap inactive bottom row swap active ec internal oscillator enabled; osc pad ignored internal oscillator disabled; osc pad enabled for input dm (1) direct mode disabled direct mode enabled dof (1) display off mode disabled display off mode enabled ib low current mode for smaller displays high current mode for larger displays pd dof hve dm mode 1 x x x chip is in power-down mode as de?ned under pd 0 1 x x all analog blocks except those required for temperature measurement are off 0 0 1 x chip is active and using the internal v lcd generator 0001 chip is active and using v dd as v lcd 0000 chip is active and using an external v lcd generator attached to v lcdin
1999 aug 24 29 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 7.17 i 2 c-bus interface 7.17.1 c haracteristics of the i 2 c- bus the i 2 c-bus is for bidirectional, two-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor. data transfer may be initiated only when the bus is not busy. 7.17.1.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as a control signal. bit transfer is illustrated in fig.15. 7.17.1.2 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line, while the clock is high is defined as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p). the start and stop conditions are illustrated in fig.16. 7.17.1.3 system con?guration the system configuration is illustrated in fig.17. transmitter: the device which sends the data to the bus receiver: the device which receives the data from the bus master: the device which initiates a transfer, generates clock signals and terminates a transfer slave: the device addressed by a master multi-master: more than one master can attempt to control the bus at the same time without corrupting the message arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted synchronization: procedure to synchronize the clock signals of two or more devices. 7.17.1.4 acknowledge each byte of 8 bits is followed by an acknowledge bit. the acknowledge bit is a high signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges must pull-down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event the transmitter must leave the data line high to enable the master to generate a stop condition. acknowledgement on the i 2 c-bus is illustrated in fig.18. handbook, full pagewidth mbc621 data line stable; data valid change of data allowed sda scl fig.15 bit transfer.
1999 aug 24 30 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 handbook, full pagewidth mbc622 sda scl p stop condition sda scl s start condition fig.16 definition of start and stop conditions. mga807 sda scl master transmitter/ receiver master transmitter slave transmitter/ receiver slave receiver master transmitter/ receiver fig.17 system configuration. handbook, full pagewidth mbc602 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master fig.18 acknowledgement on the i 2 c-bus.
1999 aug 24 31 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 7.17.2 i 2 c- bus protocol the PCF8535 is a slave receiver/transmitter. if data is to be read from the device the sdaout pad must be connected, otherwise sdaout is unused. before any data is transmitted on the i 2 c-bus, the device which should respond is addressed. four slave addresses, 0111100, 0111101, 0111110 and 0111111 are reserved for the PCF8535. the least significant bits (lsbs) of the slave address is set by connecting sa1 and sa0 to either logic 0 (v ss ) or logic 1 (v dd ). a sequence is initiated with a start condition (s) from the i 2 c-bus master which is followed by the slave address. all slaves with the corresponding address acknowledge in parallel, all the others will ignore the i 2 c-bus transfer. after the acknowledgement cycle of a write, a control byte follows which defines the destination for the forthcoming data byte and the mode for subsequent bytes. for a read, the PCF8535 will immediately start to output the requested data until a not acknowledge is transmitted by the master. the sequence should be terminated by a stop in the event that no further access is required for the time being, or by a re-start, should further access be required. for ease of operation a continuation bit, co, has been included. this bit allows the user to set-up the chip configuration and transmit ram data in one access. a data selection bit, d/ c, defines the destination for data. these bits are contained in the control byte. db5 to db0 should be set to logic 0. these bits are reserved for future expansion. table 19 co and d/ c de?nitions an example of a write access is given in fig.19. here, multiple instruction data is sent, followed by multiple display bytes. an example of a read access is given in fig.20. bit 0/1 r/ w action co 0 n.a. last control byte to be sent: only a stream of data bytes are allowed to follow; this stream may only be terminated by a stop or re-start condition 1 another control byte will follow the data byte unless a stop or re-start condition is received d/ c 0 0 data byte will be decoded and used to set up the device 1 data byte will return the contents of the currently selected status register 1 0 data byte will be stored in the display ram 1 no provision for ram read back is provided fig.19 master transmits to slave receiver; write mode. handbook, full pagewidth mgs682 s01111 s a 0 s a 1 0a acknowledgement from PCF8535 acknowledgement from PCF8535 acknowledgement from PCF8535 acknowledgement from PCF8535 acknowledgement from PCF8535 1 control byte a data byte data byte n 3 0 bytes 1 byte slave address msb . . . . . . . . . . . lsb 2n 3 0 bytes a co update data pointer co r/w 0a ap d/c d/c control byte
1999 aug 24 32 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 handbook, full pagewidth mgs683 s01111 s a 0 1a acknowledgement from PCF8535 not acknowledgement from master temp. read out value ap s a 1 slave address r/w stop condition fig.20 master reads a slaves status register. 8 limiting values (provisional) in accordance with the absolute maximum rating system (iec 134); notes 1, 2 and 3. notes 1. stresses above these values listed may cause permanent damage to the device. 2. parameters are valid over the operating temperature range unless otherwise specified. all voltages are referenced to v ss unless otherwise specified. 3. v ss =0v. 9 handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is recommended to take normal precautions appropriate to handling mos devices (see handling mos devices ). symbol parameter min. max. unit v dd supply voltage - 0.5 +7.0 v i dd supply current - 50 +50 ma v lcd lcd supply voltage - 0.5 +17.0 v i lcd lcd supply current - 50 +50 ma i ss negative supply current - 50 +50 ma v i /v o input/output voltage (any input/output) - 0.5 v dd + 0.5 v i i dc input current - 10 +10 ma i o dc output current - 10 +10 ma p tot total power dissipation per package - 300 mw p/out power dissipation per output - 30 mw t amb ambient temperature - 40 +85 c t stg storage temperature - 65 +150 c t j(max) maximum junction temperature - 150 c
1999 aug 24 33 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 10 dc characteristics v dd = 4.5 to 5.5 v; v ss =0v; v lcd = 4.5 to 16.0 v; t amb = - 40 to +85 c; unless otherwise speci?ed. notes 1. lcd outputs are open-circuit, inputs at v dd or v ss , bus inactive, f osc = typical internal oscillator frequency. 2. conditions are: v dd1 to v dd3 = 5.0 v, v lcd = 12.0 v and external v lcd . 3. power-down mode. during power-down all static currents are switched off. 4. conditions are: v dd1 to v dd3 = 5.0 v, v lcd =v dd2 and external v lcd . 5. internal v lcd generation or external v lcd . 6. conditions are: v dd1 to v dd3 = 5.0 v, v lcd = 12.0 v and voltage multiplier = 3v dd . 7. i lcd =10 m a. outputs tested one at a time. symbol parameter conditions min. typ. max. unit supplies v lcdin lcd supply voltage mux mode 1 : 65 8.0 - 16.0 v mux mode 1 : 49 8.0 - 16.0 v mux mode 1 : 34 -- 16.0 v mux mode 1 : 26 -- 16.0 v mux mode 1 : 17 -- 16.0 v i lcdin lcd supply current normal mode; notes 1 and 2 - 40 90 m a normal mode; notes 1 and 4 - 18 40 m a v lcdout generated supply voltage lcd voltage generator enabled -- 16.0 v v dd1 , v dd2 , v dd3 supply voltage 4.5 - 5.5 v i dd supply current power-down mode; notes 1, 3 and 5 - 210 m a display off mode; notes 1 and 5 ---m a normal mode; notes 1 and 6 - 160 350 m a normal mode; notes 1 and 2 - 40 90 m a logic v il low-level input voltage v ss - 0.3v dd v v ih high-level input voltage 0.7v dd - v dd v i ol low-level output current (sda) v ol = 0.4 v; v dd = 5 v 3.0 -- ma i l leakage current v i =v dd or v ss - 1 - +1 m a column and row outputs r o(col) column output resistance c0 to c132 v lcd = 12 v; note 7 -- 10 k w r o(row) row output resistance r0 to r33 v lcd = 12 v; note 7 -- 3.0 k w v bias(col) bias tolerance c0 to c132 - 100 0 +100 mv v bias(row) bias tolerance r0 to r64 - 100 0 +100 mv temperature coef?cient t cut cut point temperature t amb = - 20 to +70 c - 27 - c
1999 aug 24 34 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 11 ac characteristics v dd = 4.5 to 5.5 v; v ss =0v; v lcd = 4.5 to 16.0 v; t amb = - 40 to +85 c; unless otherwise speci?ed. notes 1. v dd1 to v dd3 =5v. 2. decoupling capacitor v lcd and v ss = 100 nf (higher capacitor size increases t su;resl and higher v dd1 to v dd3 reduces t su;resl ). 3. all timing values are valid within the operating supply voltage and ambient temperature range and are referenced to v il and v ih with an input voltage swing of v ss to v dd . 4. c b = total capacitance of one bus line in pf. symbol parameter conditions min. typ. max. unit f fr(lcd) lcd frame frequency (internal clock) 48 80 165 hz f clk(ext) external clock frequency see table 20 120 - 410 khz t w(resl) reset low pulse width 1 --m s t w(resh) reset high pulse width 5 --m s t su;resl reset low pulse set-up time after power-on notes 1 and 2 -- 30 m s t r(op) end of reset pulse to interface being operational -- 3 m s serial-bus interface; note 3 f scl scl clock frequency 0 - 400 khz t low scl clock low period 1.3 --m s t high scl clock high period 0.6 --m s t su;dat data set-up time 100 -- ns t hd;dat data hold time 0 - 0.9 m s t r scl, sda rise time note 4 20 + 0.1c b - 300 ns t f scl, sda fall time note 4 20 + 0.1c b - 300 ns c b capacitive load represented by each bus line -- 400 pf t su;sta set-up time for a repeated start condition 0.6 --m s t hd;sta start condition hold time 0.6 --m s t su;sto set-up time for stop condition 0.6 --m s t sp tolerable spike width on bus -- 50 ns t buf bus free time between a stop and start condition 1.3 --m s
1999 aug 24 35 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 handbook, full pagewidth sda mga728 sda scl t su;sta t su;sto t hd;sta t buf t low t hd;dat t high t r t f t su;dat fig.21 i 2 c-bus timing diagram. table 20 external clock frequency mux mode division ratio external clock frequency for an 80 hz frame frequency (division ratio 80 hz) 1 : 65 3168 253 khz 1 : 48 3136 251 khz 1 : 33 2720 218 khz 1 : 26 2592 207 khz 1 : 17 2592 207 khz
1999 aug 24 36 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 12 reset timing handbook, full pagewidth mgs684 t su;resl t w(resl) t w(resh) t w(resh) t w(resl) t w(resl) t w(resl) t r(op) v dd res v dd res sda, scl res fig.22 reset timing.
1999 aug 24 37 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 13 application information table 21 programming example for PCF8535 step serial bus byte display (1) operation 1 start condition blank start 2 db7 0 db6 1 db5 1 db4 1 db3 1 db2 sa1 db1 sa0 db0 0 blank slave address, r/ w=0 3 db7 0 db6 0 db5 0 db4 0 db3 0 db2 0 db1 0 db0 0 blank control byte, co = 0, d/ c=0 4 db7 0 db6 0 db5 0 db4 0 db3 0 db2 0 db1 0 db0 1 blank h[2:0] independent command; select function and ram command page h[1:0] = 111 5 db7 0 db6 0 db5 0 db4 1 db3 0 db2 0 db1 0 db0 0 blank function and ram command page; pd = 0, v = 0 6 db7 0 db6 0 db5 0 db4 0 db3 1 db2 1 db1 1 db0 0 blank function and ram command page; select display setting command page h[1:0] = 110 7 db7 0 db6 0 db5 0 db4 1 db3 0 db2 0 db1 1 db0 0 blank display setting command page; set bias system to 1 / 9 bs[2:0] = 010 8 db7 0 db6 0 db5 0 db4 0 db3 0 db2 1 db1 1 db0 0 blank display setting command page; set normal mode (d = 1, e = 0) 9 db7 1 db6 0 db5 0 db4 0 db3 0 db2 1 db1 0 db0 0 blank select mux rate 1 : 65 10 db7 0 db6 0 db5 0 db4 0 db3 0 db2 0 db1 0 db0 1 blank h[2:0] independent command; select function and ram command page h[1:0] = 111 11 db7 0 db6 0 db5 0 db4 0 db3 1 db2 1 db1 0 db0 1 blank function and ram command page; select hv-gen command page h[1:0] = 101 12 db7 0 db6 0 db5 0 db4 0 db3 1 db2 0 db1 0 db0 1 blank hv-gen command page; select voltage multiplication factor 3 s[1:0] = 01 13 db7 0 db6 0 db5 0 db4 1 db3 0 db2 0 db1 1 db0 0 blank hv-gen command page; select temperature coef?cient 2 tc[2:0] = 010 14 db7 1 db6 0 db5 1 db4 0 db3 1 db2 0 db1 0 db0 0 blank hv-gen command page; set v lcd = 12.02 v; v op [6:0] = 0101000 15 db7 0 db6 0 db5 0 db4 0 db3 0 db2 1 db1 1 db0 1 blank hv-gen command page; select high v lcd programming range (prs = 1), voltage multiplier on (hve = 1) 16 start condition blank repeat start 17 db7 0 db6 1 db5 1 db4 1 db3 1 db2 sa1 db1 sa0 db0 0 blank slave address, r/ w=0 18 db7 0 db6 1 db5 0 db4 0 db3 0 db2 0 db1 0 db0 0 blank control byte, co = 0, d/ c=1
1999 aug 24 38 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 19 db7 0 db6 0 db5 0 db4 1 db3 1 db2 1 db1 1 db0 1 data write; y, x are initialized to logic 0 by default, so they are not set here 20 db7 0 db6 0 db5 0 db4 0 db3 0 db2 1 db1 0 db0 1 data write 21 db7 0 db6 0 db5 0 db4 0 db3 0 db2 1 db1 1 db0 1 data write 22 db7 0 db6 0 db5 0 db4 0 db3 0 db2 0 db1 0 db0 0 data write 23 db7 0 db6 0 db5 0 db4 1 db3 1 db2 1 db1 1 db0 1 data write 24 db7 0 db6 0 db5 0 db4 0 db3 0 db2 1 db1 0 db0 0 data write 25 db7 0 db6 0 db5 0 db4 1 db3 1 db2 1 db1 1 db0 1 data write, last data, stop transmission 26 start condition repeat start 27 db7 0 db6 1 db5 1 db4 1 db3 1 db2 sa1 db1 sa0 db0 0 slave address, r/ w=0 step serial bus byte display (1) operation mgs405 mgs406 mgs407 mgs408 mgs409 mgs410 mgs411 mgs411
1999 aug 24 39 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 28 db7 1 db6 0 db5 0 db4 0 db3 0 db2 0 db1 0 db0 0 control byte, co = 1, d/ c=0 29 db7 0 db6 0 db5 0 db4 0 db3 0 db2 0 db1 0 db0 1 h[1:0] independent command; select function and ram command page h[1:0] = 111 30 db7 1 db6 0 db5 0 db4 0 db3 0 db2 0 db1 0 db0 0 control byte, co = 1, d/ c=0 31 db7 0 db6 0 db5 0 db4 0 db3 1 db2 1 db1 1 db0 0 function and ram command page; select display setting command page h[1:0] = 110 32 db7 1 db6 0 db5 0 db4 0 db3 0 db2 0 db1 0 db0 0 control byte, co = 1, d/ c=0 33 db7 0 db6 0 db5 0 db4 0 db3 1 db2 1 db1 0 db0 1 display control; set inverse video mode (d = 1, e = 1) 34 db7 1 db6 0 db5 0 db4 0 db3 0 db2 0 db1 0 db0 0 control byte, co = 1, d/ c=0 35 db7 1 db6 0 db5 0 db4 0 db3 0 db2 0 db1 0 db0 0 set x address of ram; set address to 0000000 step serial bus byte display (1) operation mgs411 mgs411 mgs411 mgs411 mgs411 mgs412 mgs412 mgs412
1999 aug 24 40 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 note 1. assumes the display ram was previously empty. the pinning of the PCF8535 is optimized for single plane wiring e.g. for chip-on-glass display modules. display size: 65 133 pixels. 36 db7 0 db6 1 db5 0 db4 0 db3 0 db2 0 db1 0 db0 0 control byte, co = 0, d/ c=1 37 db7 0 db6 0 db5 0 db4 0 db3 0 db2 0 db1 0 db0 0 data write 38 db7 0 db6 0 db5 0 db4 0 db3 0 db2 0 db1 0 db0 0 data write 39 db7 0 db6 0 db5 0 db4 0 db3 0 db2 0 db1 0 db0 0 data write 40 stop condition end of transfer step serial bus byte display (1) operation mgs412 mgs414 mgs685 mgs686
1999 aug 24 41 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 handbook, full pagewidth mgs687 3 display 65 133 pixels v dd1 to v dd3 i/o v ss1, v ss2 c ext r supply r common r i/o v lcd PCF8535 133 33 32 fig.23 application diagram (cog). the required minimum value for the external capacitors in an application with the PCF8535 are: c ext for v lcd , v ss1 and v ss2 = 100 nf (min.) (recommended 470 nf to 1 m f); c ext for v dd1 to v dd3 , v ss1 and v ss2 = 470 nf (recommended capacitor larger than the capacitor for v lcd , v ss1 and v ss2 ). higher capacitor values are recommended for ripple reduction. for cog applications the recommended ito track resistance is to be minimized for the i/o and supply connections. maximum values for supply tracks (r supply ) are 120 w . maximum values for the common resistance to the source, (r common ) are 120 w . higher track resistance reduces performance and increases current consumption. three i/o lines are required for the cog module; sda, scl and res (optional). other signals may be fixed on the module to appropriate levels. r i/o should also be minimized. in particular, if the i 2 c-bus acknowledge or temperature read back is required, the r i/o for the sda line must be carefully considered in conjunction with the value of the external pull-up resistor.
1999 aug 24 42 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 14 bonding pad locations table 22 bonding pad locations all x and y coordinates are referenced to the centre of the chip (dimensions in m m; see fig.27). symbol pad x y dummy 1 - 1050 - 6156 bump/align 1 2 +1050 - 6081 r0 3 +1050 - 5985 r1 4 +1050 - 5915 r2 5 +1050 - 5845 r3 6 +1050 - 5775 r4 7 +1050 - 5705 r5 8 +1050 - 5635 r6 9 +1050 - 5565 r7 10 +1050 - 5495 r8 11 +1050 - 5425 r9 12 +1050 - 5355 r10 13 +1050 - 5285 r11 14 +1050 - 5215 r12 15 +1050 - 5145 r13 16 +1050 - 5075 r14 17 +1050 - 5005 r15 18 +1050 - 4935 c0 19 +1050 - 4725 c1 20 +1050 - 4655 c2 21 +1050 - 4585 c3 22 +1050 - 4515 c4 23 +1050 - 4445 c5 24 +1050 - 4305 c6 25 +1050 - 4235 c7 26 +1050 - 4165 c8 27 +1050 - 4095 c9 28 +1050 - 4025 c10 29 +1050 - 3955 c11 30 +1050 - 3885 c12 31 +1050 - 3815 c13 32 +1050 - 3745 c14 33 +1050 - 3675 c15 34 +1050 - 3605 c16 35 +1050 - 3535 c17 36 +1050 - 3465 c18 37 +1050 - 3395 c19 38 +1050 - 3325 c20 39 +1050 - 3255 c21 40 +1050 - 3185 c22 41 +1050 - 3115 c23 42 +1050 - 3045 c24 43 +1050 - 2975 c25 44 +1050 - 2905 c26 45 +1050 - 2835 c27 46 +1050 - 2765 c28 47 +1050 - 2695 c29 48 +1050 - 2625 c30 49 +1050 - 2555 c31 50 +1050 - 2485 c32 51 +1050 - 2415 c33 52 +1050 - 2345 c34 53 +1050 - 2275 c35 54 +1050 - 2205 c36 55 +1050 - 2135 c37 56 +1050 - 1995 c38 57 +1050 - 1925 c39 58 +1050 - 1855 c40 59 +1050 - 1785 c41 60 +1050 - 1715 c42 61 +1050 - 1645 c43 62 +1050 - 1575 c44 63 +1050 - 1505 c45 64 +1050 - 1435 c46 65 +1050 - 1365 c47 66 +1050 - 1295 c48 67 +1050 - 1225 c49 68 +1050 - 1155 c50 69 +1050 - 1085 c51 70 +1050 - 1015 c52 71 +1050 - 945 c53 72 +1050 - 875 c54 73 +1050 - 805 c55 74 +1050 - 735 c56 75 +1050 - 665 c57 76 +1050 - 595 c58 77 +1050 - 525 c59 78 +1050 - 455 symbol pad x y
1999 aug 24 43 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 c60 79 +1050 - 385 c61 80 +1050 - 315 c62 81 +1050 - 245 c63 82 +1050 - 175 c64 83 +1050 - 105 c65 84 +1050 - 35 c66 85 +1050 +35 c67 86 +1050 +105 c68 87 +1050 +175 c69 88 +1050 +315 c70 89 +1050 +385 c71 90 +1050 +455 c72 91 +1050 +525 c73 92 +1050 +595 c74 93 +1050 +665 c75 94 +1050 +735 c76 95 +1050 +805 c77 96 +1050 +875 c78 97 +1050 +945 c79 98 +1050 +1015 c80 99 +1050 +1085 c81 100 +1050 +1155 c82 101 +1050 +1225 c83 102 +1050 +1295 c84 103 +1050 +1365 c85 104 +1050 +1435 c86 105 +1050 +1505 c87 106 +1050 +1575 c88 107 +1050 +1645 c89 108 +1050 +1715 c90 109 +1050 +1785 c91 110 +1050 +1855 c92 111 +1050 +1925 c93 112 +1050 +1995 c94 113 +1050 +2065 c95 114 +1050 +2135 c96 115 +1050 +2205 c97 116 +1050 +2275 c98 117 +1050 +2345 c99 118 +1050 +2415 c100 119 +1050 +2485 symbol pad x y c101 120 +1050 +2625 c102 121 +1050 +2695 c103 122 +1050 +2765 c104 123 +1050 +2835 c105 124 +1050 +2905 c106 125 +1050 +2975 c107 126 +1050 +3045 c108 127 +1050 +3115 c109 128 +1050 +3185 c110 129 +1050 +3255 c111 130 +1050 +3325 c112 131 +1050 +3395 c113 132 +1050 +3465 c114 133 +1050 +3535 c115 134 +1050 +3605 c116 135 +1050 +3675 c117 136 +1050 +3745 c118 137 +1050 +3815 c119 138 +1050 +3885 c120 139 +1050 +3955 c121 140 +1050 +4025 c122 141 +1050 +4095 c123 142 +1050 +4165 c124 143 +1050 +4235 c125 144 +1050 +4305 c126 145 +1050 +4375 c127 146 +1050 +4445 c128 147 +1050 +4515 c129 148 +1050 +4585 c130 149 +1050 +4655 c131 150 +1050 +4725 c132 151 +1050 +4795 r47 152 +1050 +5005 r46 153 +1050 +5075 r45 154 +1050 +5145 r44 155 +1050 +5215 r43 156 +1050 +5285 r42 157 +1050 +5355 r41 158 +1050 +5425 r40 159 +1050 +5495 r39 160 +1050 +5565 symbol pad x y
1999 aug 24 44 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 r38 161 +1050 +5635 r37 162 +1050 +5705 r36 163 +1050 +5775 r35 164 +1050 +5845 r34 165 +1050 +5915 r33 166 +1050 +5985 bump/align 2 167 +1050 +6081 dummy 168 - 1050 +6094 r48 169 - 1050 +5954 r49 170 - 1050 +5884 r50 171 - 1050 +5814 r51 172 - 1050 +5744 r52 173 - 1050 +5674 r53 174 - 1050 +5604 r54 175 - 1050 +5534 r55 176 - 1050 +5464 r56 177 - 1050 +5394 r57 178 - 1050 +5324 r58 179 - 1050 +5254 r59 180 - 1050 +5184 r60 181 - 1050 +5114 r61 182 - 1050 +5044 r62 183 - 1050 +4974 r63 184 - 1050 +4904 r64 185 - 1050 +4834 bump/align 3 186 - 1050 +4414 dummy 187 - 1050 +4274 dummy 188 - 1050 +3996 dummy 189 - 1050 +3574 osc 190 - 1050 +3154 v lcdin 191 - 1050 +2874 v lcdin 192 - 1050 +2804 v lcdin 193 - 1050 +2734 v lcdin 194 - 1050 +2664 v lcdin 195 - 1050 +2594 v lcdin 196 - 1050 +2524 v lcdout 197 - 1050 +2384 v lcdout 198 - 1050 +2314 v lcdout 199 - 1050 +2244 v lcdout 200 - 1050 +2174 v lcdout 201 - 1050 +2104 symbol pad x y v lcdout 202 - 1050 +2034 v lcdout 203 - 1050 +1964 v lcdsence 204 - 1050 +1894 dummy 205 - 1050 +1544 dummy 206 - 1050 +1264 res 207 - 1050 +914 t3 208 - 1050 +704 t2 209 - 1050 +494 t1 210 - 1050 +284 v dd2 211 - 1050 +144 v dd2 212 - 1050 +74 v dd2 213 - 1050 +4 v dd2 214 - 1050 - 66 v dd2 215 - 1050 - 136 v dd2 216 - 1050 - 206 v dd2 217 - 1050 - 276 v dd2 218 - 1050 - 346 v dd3 219 - 1050 - 416 v dd3 220 - 1050 - 486 v dd3 221 - 1050 - 556 v dd3 222 - 1050 - 626 v dd1 223 - 1050 - 696 v dd1 224 - 1050 - 766 v dd1 225 - 1050 - 836 v dd1 226 - 1050 - 906 v dd1 227 - 1050 - 976 v dd1 228 - 1050 - 1046 dummy 229 - 1050 - 1186 sda 230 - 1050 - 1466 sda 231 - 1050 - 1536 sdaout 232 - 1050 - 1886 sa1 233 - 1050 - 2166 sa0 234 - 1050 - 2376 v ss2 235 - 1050 - 2586 v ss2 236 - 1050 - 2656 v ss2 237 - 1050 - 2726 v ss2 238 - 1050 - 2796 v ss2 239 - 1050 - 2866 v ss2 240 - 1050 - 2936 v ss2 241 - 1050 - 3006 v ss2 242 - 1050 - 3076 symbol pad x y
1999 aug 24 45 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 table 23 alignment marks table 24 bonding pads v ss1 243 - 1050 - 3146 v ss1 244 - 1050 - 3216 v ss1 245 - 1050 - 3286 v ss1 246 - 1050 - 3356 v ss1 247 - 1050 - 3426 v ss1 248 - 1050 - 3496 v ss1 249 - 1050 - 3566 v ss1 250 - 1050 - 3636 t5 251 - 1050 - 3846 t4 252 - 1050 - 4056 dummy 253 - 1050 - 4126 scl 254 - 1050 - 4406 scl 255 - 1050 - 4476 bump/align 4 256 - 1050 - 4605 r32 257 - 1050 - 4826 r31 258 - 1050 - 4896 r30 259 - 1050 - 4966 r29 260 - 1050 - 5036 r28 261 - 1050 - 5106 r27 262 - 1050 - 5176 r26 263 - 1050 - 5246 r25 264 - 1050 - 5316 r24 265 - 1050 - 5386 r23 266 - 1050 - 5456 r22 267 - 1050 - 5526 r21 268 - 1050 - 5596 r20 269 - 1050 - 5666 r19 270 - 1050 - 5736 r18 271 - 1050 - 5806 r17 272 - 1050 - 5876 r16 273 - 1050 - 5946 symbol pad x y marks x y alignment mark 1 - 1045 - 4720 alignment mark 2 - 1045 +4620 alignment mark 3 +1045 +6196 alignment mark 4 +1045 - 6196 dummy bump/alignment mark 1 +1050 - 6081 dummy bump/alignment mark 2 +1050 +6081 dummy bump/alignment mark 3 - 1050 +4414 dummy bump/alignment mark 4 - 1050 - 4605 bottom left - 1180 - 6330 top right +1180 +6330 pad size unit pad pitch minimum 70 m m pad size; al 62 100 m m cbb opening 36 76 m m bump dimensions 50 90 17.5 ( 5) m m wafer thickness (including bumps) maximum 381 m m
1999 aug 24 46 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 mgs688 handbook, halfpage x centre y centre 100 m m fig.24 shape of alignment mark. mgs689 handbook, halfpage x centre y centre 80 m m fig.25 shape of dummy bump/alignment mark. handbook, halfpage mgs690 12.66 mm pitch 2.36 mm PCF8535 fig.26 bonding pads.
1999 aug 24 47 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 handbook, full pagewidth mgs693 r48 r64 t2 t1 t3 scl sda sdaout v ss1 v ss2 osc v lcdin v lcdout v lcdsense v dd1 v dd3 v dd2 sa0 sa1 pc8535 t4 t5 x y 0, 0 r15 . . . c0 . . . r0 dummy bump alignment mark . . . res r33 . . . c132 . . . r47 . . . . . . . . . r32 r16 pad one . . . . . . fig.27 bonding pad location (viewed from bump side). the position of the bonding pads is not to scale.
1999 aug 24 48 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 15 device protection diagram handbook, full pagewidth mgs672 v dd1 v dd1 v ss1 v ss2 v ss1 scl, sda, sdaout v ss1 v ss1 v dd1 osc, sa0, sa1, t4, t5, res v ss1 v dd1 t1, t2, t3 pads 223 to 228 pads 211 to 218 pads v dd3 v ss1 pads 219 to 222 v lcdout v ss1 pads 197 to 203 v lcdin , v lcdsense v ss1 pads 191 to 196, 204 pads 254, 255, 230 to 232 pads 190, 233, 234, 252, 251, 207 pads 208 to 210 v ss1 v lcdin pads 3 to 166, 169 to 185, 257 to 273 pads 243 to 250 pads 235 to 242 v dd2 v ss1 v ss2 fig.28 device diode protection diagram.
1999 aug 24 49 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 16 tray information handbook, full pagewidth mgs691 d c a x y f e b fig.29 tray details. the dimensions are given in table 25. table 25 dimensions handbook, halfpage mgs692 pc8535-1 fig.30 tray alignment. the orientation of the ic in a pocket is indicated by the position of the ic type name on the die surface with respect to the chamfer on the upper left corner of the tray. refer to the bonding pad location diagram for the orientating and position of the type name on the die surface. dim. description value a pocket pitch in x direction 14.88 mm b pocket pitch in y direction 4.06 mm c pocket width in x direction 12.76 mm d pocket width in y direction 2.46 mm e tray width in x direction 50.8 mm f tray width in y direction 50.8 mm x number of pockets in x direction 3 y number of pockets in y direction 11
1999 aug 24 50 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 17 definitions 18 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 19 purchase of philips i 2 c components 20 bare die disclaimer all die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of philips' delivery. if there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. there is no post waffle pack testing performed on individual die. although the most modern processes are utilized for wafer sawing and die pick and place into waffle pack carriers, philips semiconductors has no control of third party procedures in the handling, packing or assembly of the die. accordingly, philips semiconductors assumes no liability for device functionality or performance of the die or systems after handling, packing or assembly of the die. it is the responsibility of the customer to test and qualify their application in which the die is used. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1999 aug 24 51 philips semiconductors objective speci?cation 65 133 pixel matrix driver PCF8535 notes
? philips electronics n.v. sca all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. internet: http://www.semiconductors.philips.com 1999 67 philips semiconductors C a worldwide company for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 3 figtree drive, homebush, nsw 2140, tel. +61 2 9704 8141, fax. +61 2 9704 8139 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101 1248, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 20 0733, fax. +375 172 20 0773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 68 9211, fax. +359 2 68 9102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 800 943 0087 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: sydhavnsgade 23, 1780 copenhagen v, tel. +45 33 29 3333, fax. +45 33 29 3905 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615 800, fax. +358 9 6158 0920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 4099 6161, fax. +33 1 4099 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 2353 60, fax. +49 40 2353 6300 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, via casati, 23 - 20052 monza (mi), tel. +39 039 203 6838, fax +39 039 203 6800 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5057 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381, fax +9-5 800 943 0087 middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 58088 newville 2114, tel. +27 11 471 5401, fax. +27 11 471 5398 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2886, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: yukari dudullu, org. san. blg., 2.cad. nr. 28 81260 umraniye, istanbul, tel. +90 216 522 1500, fax. +90 216 522 1813 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 208 730 5000, fax. +44 208 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381, fax. +1 800 943 0087 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 62 5344, fax.+381 11 63 5777 printed in the netherlands 465006/01/pp 52 date of release: 1999 aug 24 document order number: 9397 750 06201

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